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ADL5205ACPZ-R7 Scheda tecnica(PDF) 5 Page - Analog Devices

Il numero della parte ADL5205ACPZ-R7
Spiegazioni elettronici  Dual, 35 dB Range, 1 dB Step Size DGA
PDF  31 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

ADL5205ACPZ-R7 Scheda tecnica(HTML) 5 Page - Analog Devices

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Data Sheet
ADL5205
Rev. A | Page 5 of 31
TIMING SPECIFICATIONS
Table 2. SPI Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
CSA or CSB to SCLK Setup Time
t
CS
20
ns
SDIO to SCLK Setup Time
tDS
10
ns
SCLK to SDIO Hold Time
tDH
10
ns
SCLK Pulse Width
tPW
25
ns
SCLK Cycle Time
tSCLK
50
ns
SCLK to CSA or CSB Setup Time
tCH
10
ns
SCLK to SDIO Output Valid Delay
tDV
20
ns
During readback
Timing Diagrams
SCLK
___ ___
CSA, CSB
SDIO
tSCLK
tCS
tDS tDH
tPW
tCH
DNC
DNC
DNC
DNC
DNC
DNC
DNC
R/W
FA1
FA0
D5
D4
D3
D2
D1
D0
tDV
Figure 2. SPI Interface Read/Write Mode Timing Diagram
UPDN_DAT_x
UPDN_CLK_x
UP
tPW
tDS
tDH
tDH
tDS
tDS
DOWN
RESET
Figure 3. Up/Down Gain Control Timing Diagram
LATCHA,
LATCHB
A5 TO A0
B5 TO B0
tDH
Figure 4. Parallel Mode Timing Diagram



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