M30302FAPFP datasheet(14/57 Pages) RENESAS

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M16C/30P Group

2. Central Processing Unit (CPU)

Rev.1.22

Mar 30, 2007

Page 14 of 53

REJ03B0088-0122

Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a

Figure 2.1

Central Processing Unit Register

2.1

Data Registers (R0, R1, R2 and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are

the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data

Data Registers (1)

Address Registers (1)

Frame Base Registers (1)

Program Counter

Interrupt Table Register

User Stack Pointer

Interrupt Stack Pointer

Static Base Register

Flag Register

NOTES:

1. These registers comprise a register bank. There are two register banks.

R0H

b15

b8 b7

INTBH

USP

ISP

IPL

R0L

R1H

R1L

b31

b19

INTBL

b15

b19

b15

FLG

b15

Reserved Area

Carry Flag

Debug Flag

Zero Flag

Sign Flag

Overflow Flag

Interrupt Enable Flag

Stack Pointer Select Flag

Reserved Area

Processor Interrupt Priority Level

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