M34571GD datasheet(57/126 Pages) RENESAS

57 / 126 page

Rev.1.02

May 25, 2007

Page 57 of 124

REJ03B0179-0102

4571 Group

(11)P21/INT1 pin

(1) Bit 3 of register I2

When the input of the P21/INT1 pin is controlled with the

bit 3 of register I2 in software, be careful about the

following notes.

• Depending on the input state of the P21/INT1 pin, the external

1 interrupt request flag (EXF1) may be set when the bit 3 of

unexpected interrupt, clear the bit 1 of register V1 to “0” (refer

to (1) in Figure 58) and then, change the bit 3 of register I2.

In addition, execute the SNZ1 instruction to clear the EXF1

flag to “0” after executing at least one instruction (refer to (2)

in Figure 58).

Also, set the NOP instruction for the case when a skip is

performed with the SNZ1 instruction (refer to (3) in Figure

58).

Fig 58. External 1 interrupt program example-1

(2) Bit 3 of register I2

When the bit 3 of register I2 is cleared to “0”, the RAM

back-up mode is selected and the input of INT1 pin is

disabled, be careful about the following notes.

• When the INT1 pin input is disabled (register I23 = “0”), set

the key-on wakeup of INT1 pin to be invalid (register L20 =

“0”) before system enters to the RAM back-up mode. (refer to

(1) in Figure 59)

Fig 59. External 1 interrupt program example-2

(3) Bit 2 of register I2

When the interrupt valid waveform of the P21/INT1 pin is

changed with the bit 2 of register I2 in software, be careful

about the following notes.

• Depending on the input state of the P21/INT1 pin, the external

1 interrupt request flag (EXF1) may be set when the bit 2 of

unexpected interrupt, clear the bit 1 of register V1 to “0” (refer

to (1) in Figure 60) and then, change the bit 2 of register I2 is

changed.

In addition, execute the SNZ1 instruction to clear the EXF1

flag to “0” after executing at least one instruction (refer to (2)

in Figure 60).

Also, set the NOP instruction for the case when a skip is

performed with the SNZ1 instruction (refer to (3) in Figure

60).

Fig 60. External 1 interrupt program example-3

•

; (

××0×2)

TV1A

; The SNZ1 instruction is valid ...... (1)

; (1

×××2)

TI1A

; Control of INT1 pin input is changed

NOP

...................................................... (2)

SNZ0

; The SNZ1 instruction is executed

(EXF1 flag cleared)

NOP

...................................................... (3)

•

×: these bits are not used here.

•

; (

×0××2)

TL1A

; INT1 key-on wakeup disabled .....(1)

EPOF

POF

; RAM back-up

•

×: these bits are not used here.

•

; (

××0×2)

TV1A

; The SNZ1 instruction is valid ......(1)

; (1

×××2)

TI1A

; Interrupt valid waveform is changed

NOP

.......................................................(2)

SNZ0

; The SNZ1 instruction is executed

(EXF1 flag cleared)

NOP

.......................................................(3)

•

×: these bits are not used here.

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