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M34571GD Scheda tecnica(PDF) 116 Page - Renesas Technology Corp

Il numero della parte M34571GD
Spiegazioni elettronici  SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PDF  126 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M34571GD Scheda tecnica(HTML) 116 Page - Renesas Technology Corp

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Rev.1.02
May 25, 2007
Page 116 of 124
REJ03B0179-0102
4571 Group
Skip condition
Detailed description
−−
Transfers the contents of key-on wakeup control register K0 to register A.
−−
Transfers the contents of register A to key-on wakeup control register K0.
−−
Transfers the contents of key-on wakeup control register K1 to register A.
−−
Transfers the contents of register A to key-on wakeup control register K1.
−−
Transfers the contents of key-on wakeup control register K2 to register A.
−−
Transfers the contents of register A to key-on wakeup control register K2.
−−
Transfers the contents of key-on wakeup control register L1 to register A.
−−
Transfers the contents of register A to key-on wakeup control register L1.
−−
Transfers the contents of clock control register MR to register A.
−−
Transfers the contents of register A to clock control register MR.
−−
No operation; Adds 1 to program counter value, and others remain unchanged.
−−
Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF
instruction.
Operations of all functions are stopped.
−−
Makes the immediate after POF instruction valid by executing the EPOF instruction.
(P) = 1
−
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P flag is “0”.
(WDF1) = 1
Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1”. When the
WDF1 flag is “0”, executes the next instruction. Also, stops the watchdog timer function when executing the
WRST instruction immediately after the DWDT instruction.
−−
Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
−−
System reset occurs.
−−
Clears (0) to the high-order bit reference enable flag UPTF.
−−
Sets (1) to the high-order bit reference enable flag UPTF.
V23 = 0 : (VDF) = 1
−
When V23 = 0 : Skips the next instruction when voltage detector interrupt request flag VDF is “1”. The VDF
flag is not cleared to “0“. When the VDF flag is “0”, executes the next instruction.
When V23 = 1 : This instruction is equivalent to the NOP instruction.
−−
Sets referring data area to pages 0 to 63 when the TABP p instruction is executed. This instruction is valid
only for the TABP p instruction.
−−
Sets referring data area to pages 64 to 127 when the TABP p instruction is executed. This instruction is valid
only for the TABP p instruction.



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