10-Bit LVDS Serializer

6

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Typical Operating Characteristics

28

31

32

33

30

29

34

3.0

3.3

3.1

3.2

3.4

3.5

3.6

WORST-CASE PATTERN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

TCLK = 40MHz

PIN

NAME

FUNCTION

1–7, 14, 15, 16

IN3–IN9, IN0,

IN1, IN2

LVCMOS/LVTTL Data Inputs. Data is loaded into a 10-bit latch by the rising TCLK edge. Each

input is internally pulled to ground.

8

TCLK

LVCMOS/LVTTL Reference Clock Input. Accepts a 16MHz to 40MHz clock. TCLK provides a

frequency reference to the PLL and strobes parallel data into the input latch on the rising edge.

9, 12

GND

Ground

10

OUT-

Inverting Bus LVDS Differential Output

11

OUT+

Noninverting Bus LVDS Differential Output

13

Power-Supply Input. Bypass to ground with a 0.1µF capacitor and a 0.001µF capacitor. Place the

—

EP

Exposed Pad. Solder EP to ground for improved heat dissipation.