H838024 datasheet(16/697 Pages) RENESAS

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Rev. 7.00 Mar 10, 2005 page xvi of xlii

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6.8.1 Program/

Program-Verify

169

Description amended

4. Consecutively transfer 128 bytes of data in byte units from

the reprogramming data area or additional-programming data

area to the flash memory. The program address and 128-byte

data are latched in the flash memory. The lower 8 bits of the

start address in the flash memory destination area must be H'00

or H'80.

Do not use RTS instruction from data transfer to setting P bit to

1. (This does not apply to the HD64F38124 and HD64F38122.)

7. For a dummy write to a verify address, write 1-byte data

H'FF to an address whose lower 1 bit is b'0. Verify data can be

read in word size from the address to which a dummy write was

performed.

Do not use RTS instruction from dummy write to verify data

read. (This does not apply to the HD64F38124 and

HD64F38122.)

6.8.2 Erase/

Erase-Verify

172

Description amended

5. For a dummy write to a verify address, write 1-byte data

H'FF to an address whose lower 1 bit is b'0. Verify data can be

read in word size from the address to which a dummy write was

performed.

Do not use RTS instruction from dummy write to verify data

read. (This does not apply to the HD64F38124 and

HD64F38122.)

6.10.1 Socket

Adapter

175

Description amended

The socket adapter converts the pin allocation of the

HD64F38024, HD64F38024R, HD64F38124, and HD64F38122

to that of the discrete flash memory HN28F101. The address of

the on-chip flash memory is H'0000 to H'7FFF. Figure 6.12(1)

shows a socket-adapter-pin correspondence diagram of the

HD64F38024 and HD64F38024R. Figure 6.12(2) shows a

socket-adapter-pin correspondence diagram of the

HD64F38124 and HD64F38122.

6.10.2 Programmer

Mode Commands

Figure 6.12(2)

Socket Adapter Pin

Correspondence

Diagram

(HD64F38124,

HD64F38122)

178

Title and figure amended

HD64F38124, HD64F38122

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