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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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CS5366 Scheda tecnica(PDF) 17 Page - Cirrus Logic |
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CS5366 Scheda tecnica(HTML) 17 Page - Cirrus Logic |
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17 / 41 page  DS626F2 17 CS5366 SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL =30pF Notes: 1. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. Figure 5. I²C Timing Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RST Rising Edge to Start tirs 600 - ns Bus Free Time Between Transmissions tbuf 4.7 µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 µs Clock Low time tlow 4.7 Clock High Time thigh 4.0 Setup Time for Repeated Start Condition tsust 4.7 SDA Hold Time from SCL Falling (Note 1) thdd 0 SDA Setup time to SCL Rising tsud 600 ns Rise Time of SCL and SDA trc -1 µs Fall Time SCL and SDA tfc -300 ns Setup Time for Stop Condition tsusp 4.7 - µs Acknowledge Delay from SCL Falling tack 300 1000 ns t buf t hdst t lo w t hdd t high t sud Stop Start SD A SCL t irs RS T t hdst t rc t fc t sust t susp Start Stop Re pe at e d t rd t fd t ack |
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