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FS2304M Scheda tecnica(PDF) 80 Page - NXP Semiconductors |
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FS2304M Scheda tecnica(HTML) 80 Page - NXP Semiconductors |
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80 / 230 page ![]() NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers aaa-051466 WD_ERR_LIMIT = 11 WD_ERR_LIMIT = 10 WD_ERR_LIMIT = 01 0 0 1 2 3 4 WD refresh NOT OK WD refresh OK WD refresh OK 0 1 2 3 4 5 6 WD refresh NOT OK WD refresh NOT OK 2 1 WD OFF WD OFF WD OFF WD_ERR_LIMIT = 00 WD refresh OK WD refresh OK WD refresh OK WD refresh OK 0 1 2 3 4 5 6 WD refresh OK WD refresh OK 7 8 WD refresh NOT OK WD refresh OK WD OFF WD refresh OK WD refresh OK WD refresh OK WD refresh OK WD refresh OK WD refresh OK WD refresh OK WD refresh OK WD refresh OK WD refresh OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK WD refresh NOT OK Figure 45. Watchdog error counter configurations 19.2.3 Watchdog refresh counter The watchdog refresh counter is used to decrement the fault error counter. Each time the watchdog is properly refreshed, the watchdog refresh counter is incremented by ’1’. Each time the watchdog refresh counter reaches its maximum value (‘6’ by default). If the next WD refresh is also good, the fault error counter is decremented by ’1’. Whatever the position the watchdog refresh counter is in, each time there is a wrong refresh watchdog, the watchdog refresh counter is reset to ’0’. To allow flexibility in the application, the maximum value of this watchdog refresh counter is configurable with the WD_RFR_LIMIT[1:0] bits during the INIT_FS phase. WD_RFR_LIMIT[1:0] Watchdog refresh counter value 00 (default) 6 01 4 10 2 11 1 Reset condition POR Table 38. Watchdog refresh counter limit configuration The watchdog refresh counter value can be read by the MCU for diagnostic with the WD_RFR_CNT[2:0] bits. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 80 / 230 |
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