CS8416-CSZ datasheet(9/60 Pages) CIRRUS

9 / 60 page

DS578F3

CS8416

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS

(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)

Notes:

8. In Software Mode the active edges of OSCLK are programmable.

9. In Software Mode the polarity of OLRCK is programmable.

10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK

has changed.

11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.

Parameter

Symbol

Min

Typ

Max

Units

OSCLK/OLRCK Active Edge to SDOUT Output Valid

(Note 8)

tdpd

Master Mode

RMCK to OSCLK active edge delay

(Note 8)

tsmd

RMCK to OLRCK delay

(Note 9)

tlmd

OSCLK and OLRCK Duty Cycle

Slave Mode

OSCLK Period

tsckw

OSCLK Input Low Width

tsckl

OSCLK Input High Width

tsckh

OSCLK Active Edge to OLRCK Edge

(Notes 8,9,10)

tlrckd

OSCLK Edge Setup Before OSCLK Active-Edge (Notes 8,9,11)

tlrcks

Figure 1. Audio Port Master Mode Timing

Figure 2. Audio Port Slave Mode and Data Input

sckh

sckl

sckw

tdpd

SDOUT

(input)

lrcks

lrckd

OSCLK

OLRCK

t smd

t lmd

OS C LK

(output)

OLRC K

(output)

RM C K

(output)

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