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LPC55S2X Scheda tecnica(PDF) 90 Page - NXP Semiconductors |
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LPC55S2X Scheda tecnica(HTML) 90 Page - NXP Semiconductors |
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90 / 132 page ![]() NXP Semiconductors LPC55S2x/LPC552x 32-bit Arm Cortex®-M33 microcontroller SCK (CPOL = 0) MISO (CPHA = 1) SSEL MOSI (CPHA = 1) Tcy(clk) tDS tDH tv(Q) DATA VALID (LSB) DATA VALID tv(Q) SCK (CPOL = 1) DATA VALID (LSB) DATA VALID MISO (CPHA = 0) MOSI (CPHA = 0) tDS tDH DATA VALID (MSB) DATA VALID (MSB) DATA VALID DATA VALID (LSB) DATA VALID (LSB) tv(Q) DATA VALID (MSB) DATA VALID tv(Q) DATA VALID (MSB) DATA VALID (MSB) DATA VALID (MSB) DATA VALID (MSB) IDLE IDLE IDLE IDLE DATA VALID (MSB) Figure 19. SPI slave timing 11.12 High-Speed SPI interface (Flexcomm Interface 8) The actual SPI bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for SPI master mode (transmit/receive) is 50 Mbit/s. Excluding delays introduced by external device and PCB, the maximum supported bit rate for SPI slave receive mode is 50 Mbit/s and for SPI slave transmit mode is 25 Mbit/s. Tamb = -40 °C to 105 °C; VDD = 1.8 V to 3.6 V; CL = 10 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting = fast mode for all pins;. Parameters sampled at the 50% level of the rising or falling edge. Symbol Parameter Conditions Min Typ Max Unit SPI master tDS data set-up time 4 - - ns tDH data hold time 0 - - ns tv(Q) data output valid time 3 - 8 ns SPI slave tDS data set-up time 4 - - ns tDH data hold time 0 - - ns Table 36. SPI dynamic characteristics[1] LPC55S2X_LPC552X All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Data sheet Rev. 2.3 — 29 August 2024 Document feedback 90 / 132 |
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