PM5366-PI datasheet(42/267 Pages) PMC

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PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

Pin Name

Type

No.

Function

DS3 and E3 System Side Interface

RGAPCLK/RSCLK

[3]

RGAPCLK/RSCLK

[2]

RGAPCLK/RSCLK

[1]

Output H4

Framer Recovered Gapped Clock (RGAPCLK[3:1]).

RGAPCLK[3:1] are valid when the TEMAP-84 is

configured as DS3 or E3 framers by setting the

OPMODE_SPEx[2:0] bits in the SPE Configuration

registers and the RXGAPEN bit in the DS3 and E3

Master Unchannelized Interface Options register.

RGAPCLK[x] is the recovered clock and timing

reference for RDATO[x]. RGAPCLK[3:1] are held

either high or low during bit positions which correspond

to overhead.

Framer Recovered Clock (RSCLK[3:1]). RSCLK[3:1]

are valid when the TEMAP-84 is configured as DS3 or

E3 framers by setting the OPMODE_SPEx[2:0] bits in

the SPE Configuration registers.

RSCLK[3:1] are the recovered clocks and timing

references for RDATO[3:1], RFPO/RMFPO[3:1], and

ROVRHD[3:1].

RDATO[3]

RDATO[2]

RDATO[1]

Output H2

Framer Receive Data (RDATO[3:1]). RDATO[3:1] are

valid when the TEMAP-84 is configured as DS3 or E3

framers by setting the OPMODE_SPEx[2:0] bits in the

SPE Configuration registers. RDATO[3:1] are the

received data aligned to RFPO/RMFPO[3:1] and

ROVRHD[3:1].

RDATO[3:1] are updated on either the falling or rising

edge of the associated RGAPCLK or RSCLK,

depending on the value of the RSCLKR bit in the DS3

and E3 Master Unchannelized Interface Options

the falling edge of the associated RGAPCLK[3:1] or

RSCLK[3:1].

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