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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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AD7766-2 Scheda tecnica(PDF) 5 Page - Analog Devices |
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AD7766-2 Scheda tecnica(HTML) 5 Page - Analog Devices |
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5 / 24 page  AD7767 Rev. 0 | Page 5 of 24 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.7 V to 3.6 V, VREF = 5 V, common-mode input = VREF/2, TA = −40°C (TMIN) to +105°C (TMAX), unless otherwise noted 1 Table 3. Parameter Limit at TMIN, TMAX Unit Description DRDY Operation t1 510 ns typ MCLK rising edge to DRDY falling edge t22 100 ns min MCLK high pulse width t3 900 ns max MCLK low pulse width 265 ns typ MCLK rising edge to DRDY rising edge (AD7767) 128 ns typ MCLK rising edge to DRDY rising edge (AD7767-1) t4 71 ns typ MCLK rising edge to DRDY rising edge (AD7767-2) 294 ns typ DRDY pulse width (AD7767) 435 ns typ DRDY pulse width (AD7767-1) t5 492 ns typ DRDY pulse width (AD7767-2) tREAD3 DRDY t − t5 ns typ DRDY low period, read data during this period DRDY t 3 n × 8 × tMCLK ns typ DRDY period Read Operation t6 0 ns min DRDY falling edge to CS setup time t7 6 ns max CS falling edge to SDO three-state disabled 60 ns max Data access time after SCLK falling edge (VDRIVE = 1.7 V) 50 ns max Data access time after SCLK falling edge (VDRIVE = 2.3 V) 25 ns max Data access time after SCLK falling edge (VDRIVE = 2.7 V) t8 24 ns max Data access time after SCLK falling edge (VDRIVE = 3.0 V) t9 10 ns min SCLK falling edge to data valid hold time (VDRIVE = 3.6 V) t10 10 ns min SCLK high pulse width t11 10 ns min SCLK low pulse width tSCLK 1/t8 min Minimum SCLK period t12 6 ns max Bus relinquish time after CS rising edge t13 0 ns min CS rising edge to DRDY rising edge Read Operation with CS Low t14 0 ns min DRDY falling edge to data valid setup time t15 0 ns max DRDY rising edge to data valid hold time Daisy Chain Operation t16 1 ns min SDI valid to SCLK falling edge setup time t17 2 ns max SCLK falling edge to SDI valid hold time SYNC/PD Operation t18 1 ns typ SYNC/PD falling edge to MCLK rising edge t19 20 ns typ MCLK rising edge to DRDY rising edge going into SYNC/PD t20 1 ns min SYNC/PD rising edge to MCLK rising edge t21 510 ns typ MCLK rising edge to DRDY falling edge coming out of SYNC/PD tSETTLING3 592 × (n + 2) tMCLK Filter settling time after a reset or power-down 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.7 V. 2 t2 and t3 allow a ~90% to 10% duty cycle to be used for the MCLK input where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum MCLK frequency is 1.024 MHz. 3 n = 1 for AD7767, n = 2 for the AD7767-1, n = 4 for the AD7767-2. |
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