RM5231 datasheet(13/39 Pages) PMC

13 / 39 page

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

Document ID: PMC-2002165, Issue 1

RM5231™ Microprocessor with 32-bit System Bus Data Sheet

Released

Table 1 Integer Multiply/Divide Operations

The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed in

the Hi and Lo registers. These values can then be transferred to the general purpose register file

using the Move-from-Hi and Move-from-Lo (MFHI/MFLO) instructions.

In addition to the baseline MIPS IV integer multiply instructions, the RM5231 also implements the

3 operand multiply instruction, MUL. This instruction specifies that the multiply result go directly

to the integer register file rather than the Lo register. The portion of the multiply that would have

normally gone into the Hi register is discarded. For applications where it is known that the upper

half of the multiply result is not required, using the MUL instruction eliminates the necessity of

executing an explicit MFLO instruction.

Also included in the RM5231 are the multiply-add instructions, MADU/MAD. This instruction

multiplies two operands and adds the resulting product to the current contents of the Hi and Lo

registers. The multiply-accumulate operation is the core primitive of almost all signal processing

algorithms allowing the RM5231 to eliminate the need for a separate DSP engine in many

embedded applications.

3.8

Floating-Point Co-Processor

The RM5231 incorporates a high-performance fully pipelined floating-point co-processor which

includes a floating-point register file and autonomous execution units for multiply/add/convert and

divide/square root. The floating-point coprocessor is a tightly coupled execution unit, decoding

and executing instructions in parallel with, and in the case of floating-point loads and stores, in

cooperation with the integer unit. The superscalar capabilities of the RM5231 allow floating-point

computation instructions to issue concurrently with integer instructions.

3.9

Floating-Point Unit

The RM5231 floating-point execution unit supports single and double precision arithmetic, as

specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square root

unit and a pipelined multiply/add unit. Overlap of the divide/square root and multiply/add

operations is supported.

The RM5231 maintains fully precise floating-point exceptions while allowing both overlapped

and pipelined operations. Precise exceptions are extremely important in object-oriented

programming environments and highly desirable for debugging in any environment.

Opcode

Operand

Size

Latency

Repeat

Rate

Stall

Cycles

MULT/U,

MAD/U

16 bit

32 bit

MUL

16 bit

32 bit

DMULT,

DMULTU

any

DIV, DIVD

any

DDIV,

DDIVU

any

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