Rev. 1.1

256K X 8 BIT LOW POWER CMOS SRAM

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

Dout

Din

Data Valid

(4)

High-Z

WE#

(4)

CE#

Address

CE2

WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)

Dout

Din

Data Valid

(4)

High-Z

WE#

CE#

Address

CE2

Notes :

1.WE#, CE# must be high or CE2 must be low during all address transitions.

2.A write occurs during the overlap of a low CE#, high CE2, low WE#.

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high

impedance state.

®

February 2007

AS6C2008

10/February/07, v.1.0

Alliance Memory Inc.

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