Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

SN65MLVD080 Scheda tecnica(PDF) 5 Page - Texas Instruments

Click here to check the latest version.
Il numero della parte SN65MLVD080
Spiegazioni elettronici  8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

SN65MLVD080 Scheda tecnica(HTML) 5 Page - Texas Instruments

  SN65MLVD080 Datasheet HTML 1Page - Texas Instruments SN65MLVD080 Datasheet HTML 2Page - Texas Instruments SN65MLVD080 Datasheet HTML 3Page - Texas Instruments SN65MLVD080 Datasheet HTML 4Page - Texas Instruments SN65MLVD080 Datasheet HTML 5Page - Texas Instruments SN65MLVD080 Datasheet HTML 6Page - Texas Instruments SN65MLVD080 Datasheet HTML 7Page - Texas Instruments SN65MLVD080 Datasheet HTML 8Page - Texas Instruments SN65MLVD080 Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 28 page
background image
www.ti.com
DRIVER SWITCHING CHARACTERISTICS
SN65MLVD080
SN65MLVD082
SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
tpLH
Propagation delay time, low-to-high-level output
1
1.5
2.4
ns
tpHL
Propagation delay time, high-to-low-level output
1
1.5
2.4
ns
tr
Differential output signal rise time
1
2
ns
tf
Differential output signal fall time
See Figure 5
1
2
ns
tsk(o)
Output skew
350
ps
tsk(p)
Pulse skew (|tPHL– tPLH|)
0
150
ps
tsk(pp)
Part-to-part skew (2)
600
ps
tjit(per)
Period jitter, rms (1 standard deviation)(3)
4
ps
100 MHz clock input(4)
tjit(c-c)
Cycle-to-cycle jitter, rms
45
ps
tjit(det)
Deterministic jitter
150
ps
200 Mbps 215–1 PRBS input(5)
tjit(pp)
Peak-to-peak jitter(2)(6)
190
ps
tPZH
Enable time, high-impedance-to-high-level output
7
ns
tPZL
Enable time, high-impedance-to-low-level output
7
ns
See Figure 6
tPHZ
Disable time, high-level-to-high-impedance output
7
ns
tPLZ
Disable time, low-level-to-high-impedance output
7
ns
(1)
All typical values are at 25°C and with a 3.3-V supply voltage.
(2)
tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3)
Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4)
tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.
(5)
tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.
(6)
Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
5
Submit Documentation Feedback



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com