ST16C550IP40 datasheet(7/34 Pages) SYC

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ST16C550

Rev. 4.30

Symbol

Signal

Pin Description

type

SYMBOL DESCRIPTION

-CTS

Clear to Send (active low) - A logic 0 on the -CTS pin indicates

the modem or data set is ready to accept transmit data from

the ST16C550. Status can be tested by reading MSR bit-4.

This pin has no effect on the UART’s transmit or receive

operation.

-DSR

Data Set Ready (active low) - A logic 0 on this pin indicates

the modem or data set is powered-on and is ready for data

exchange with the UART. This pin has no effect on the

UART’s transmit or receive operation.

-DTR

Data Terminal Ready (active low) - A logic 0 on this pin

indicates that the ST16C550 is powered-on and ready. This

pin can be controlled via the modem control register.

Writing a logic 1 to MCR bit-0 will set the -DTR output to

logic 0, enabling the modem. This pin will be a logic 1 after

writing a logic 0 to MCR bit-0, or after a reset. This pin has

no effect on the UART’s transmit or receive operation.

-RI

Ring Indicator (active low) - A logic 0 on this pin indicates the

modem has received a ringing signal from the telephone

line. A logic 1 transition on this input pin will generate an

interrupt.

-RTS

Request to Send (active low) - A logic 0 on the -RTS pin

indicates the transmitter has data ready and waiting to send.

Writing a logic 1 in the modem control register (MCR bit-1)

will set this pin to a logic 0 indicating data is available. After

a reset this pin will be set to a logic 1. This pin has no effect

on the UART’s transmit or receive operation.

Receive Data - This pin provides the serial receive data

input to the ST16C550. A logic 1 indicates no data or an idle

channel. During the local loop-back mode, the RX input pin is

disabled and TX data is internally connected to the UART RX

Input, internally, see figure 12.

Transmit Data - This pin provides the serial transmit data

from the ST16C550, the TX signal will be a logic 1 during

reset, idle (no data). During the local loop-back mode, the

TX pin is set to a logic 1 and TX data is internally connected

to the UART RX Input, see figure 12.

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