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WLFO Scheda tecnica(PDF) 4 Page - Amkor Technology

Il numero della parte WLFO
Spiegazioni elettronici  Wafer level packaging applies similar processes as used in front-end wafer processing.
PDF  5 Pages
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Produttore elettronici  AMKOR [Amkor Technology]
Homepage  http://www.amkor.com
Logo AMKOR - Amkor Technology

WLFO Scheda tecnica(HTML) 4 Page - Amkor Technology

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Overview
Amkor has applied its WLFO technology know-how,
taking Wafer Level CSP (WLCSP) to the next packaging
generation: WLCSP+.
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Recon wafer is created with KGD (Known Good Die)
placed with very small distance between dies
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All solder balls are placed in the fan-in zone
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Mold compound offers 5-side mechanical die
protection (sidewalls and optional backside
protection)
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Compared to WLCSP, WLCSP+ offers an additional
50% increase in die strength
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Diced die test on wafer-level without bare die
handling
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Components can be delivered in JEDEC tray without
risk
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WLCSP manufacturing in highly efficient 300 mm
WLFO recon wafer, independent of wafer diameter
provided by the customer
Design Features
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Supports 300 mm wafer diameter
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Single/multi-layer Cu RDL, with and without Cu UBM
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Max package size: 23 x 25 mm2 (largest in the
market)
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Min package thickness: 0.4 mm (thinner under
validation)
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Plated RDL line/space width: 20/20 μm (10/10 μm
under validation)
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Bump height and pitch: 0.25 mm @ 0.5 mm (down
to 0.2 mm @ 0.4 mm under validation)
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Backside coating optional
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Standard laser marking and packing in tape and reel
Applications
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Mobile and consumer products, handsets
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Wireless connectivity including Bluetooth, WLAN,
RF, FM radio, GPS
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PMIC, PMU, high performance computing
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Analog and other ICs such as MEMS and Sensors
WLCSP+
Performance
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Electrical: Low parasitics due to short connections
(WLCSP), thick Cu- RDL and choice of dielectric
material (LTC-PI). Dependent on design and
application suitable for 10 GHz and beyond
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Thermal: Depending on die size and whether
backside die is molded/exposed (e.g., 5 x 5 mm2 die,
molded backside die: Rth = 30 K/W)
Performance Data: Reliability
6.6 x 7.1 x 0.4 mm3, 98 bumps, 500 µm pitch; WLCSP+
with 30 µm sidewall + backside mold. Stack-up: PBO/Cu
RDL/PBO/Cu UBM.
Component Level Tests
Test
Specification
Criteria
Moisture Sensitivity
Level (MSL)
IPC/JEDEC J-STD-020
MSL1 For Lead-free,
168 Hrs at 85°C/85%
RH
Temperature Cycling
(TC)
JESD22-A104,
Condition B
-55°C/125°C,
2 Cy/Hour, 1000 Cycles
High Temperature
Storage (HTS)
JESD22-A103,
Condition B
150°C, 2000 Hours
Unbiased HAST
(uHAST)
JESD22-A118,
Condition A
130°C/85% RH,
96 Hours
Board Level Tests
Test
Specification
Criteria
Drop Test
JESD22-B111
30 Drops
Temperature Cycling
on Board (TCoB)
IPC-97-01
-40°C/125°C,
1 Cy/Hour, 1000x



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