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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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STR750FV1 Scheda tecnica(PDF) 69 Page - STMicroelectronics |
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STR750FV1 Scheda tecnica(HTML) 69 Page - STMicroelectronics |
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69 / 81 page  STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters 69/81 not possible to power off the STR7x while some another I2C master node remains powered on: otherwise, the STR7x will be powered by the protection diode. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Figure 40. Typical application with I2C bus and timing diagram 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. Table 41. SDA and SCL characteristics Symbol Parameter Standard mode I2C Fast mode I2C(1) 1. fPCLK, must be at least 8 MHz to achieve max fast I 2C speed (400 kHz). Unit Min(2) 2. Data based on standard I2C protocol requirement, not tested in production. Max(2) Min(2) Max(2) tw(SCLL) SCL clock low time 4.7 1.3 µs tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 ns th(SDA) SDA data hold time 0(3) 3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 0(4) 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 900(3) tr(SDA) tr(SCL) SDA and SCL rise time 1000 20+0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 20+0.1Cb 300 th(STA) START condition hold time 4.0 0.6 µs tsu(STA) Repeated START condition setup time 4.7 0.6 tsu(STO) STOP condition setup time 4.0 0.6 µs tw(STO:STA) STOP to START condition time (bus free) 4.7 1.3 µs Cb Capacitive load for each bus line 400 400 pF REPEATED START START STOP START tf(SDA) tr(SDA) tsu(SDA) th(SDA) tf(SCK) tr(SCK) tw(SCKL) tw(SCKH) th(STA) tsu(STO) tsu(STA) tw(STO:STA) SDA SCL 4.7k Ω SDA STRT75X SCL VDD 100 Ω 100 Ω VDD 4.7k Ω I2CBUS |
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