PPC440GP-3CC466C datasheet(75/83 Pages) AMCC

75 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

DDR SDRAM MemClkOut0 and Read Clock Delay

In operation, following the receipt of an address and read command from the PPC440GP, the SDRAM generates

data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GP using a DQS

signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs

using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to

be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of

Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.

DDR SDRAM Read Data Path

Read Clock

PLB Clk

MemClkOut0(0)

TMD

TRD

TMDmin =

TMDmax =

TRDmin =

TRDmax =

850ps

2600ps

300ps

0ps

Stage 1

Stage 2

Stage 3

RDSP

PLB bus

FF,

Data

Read Select

(SDRAM0_TR1)

DQS

1/4

Cycle

Delay

PLB Clock

Programmed

Delay

Package pins

Mux

Read Clock

FF Timing:

TIS = Input setup time = 0.2ns

TIH = Input hold time = 0.1ns

TP = Propagation delay (D to Q or C to Q) =

ECC

FF: Flip-Flop

XL: Transparent Latch

0.6ns maximum

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