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POWER MANAGEMENT

SC453

Applications Information (Cont.)

PG# Output

This is an open-drain output and should be pulled up ex-

ternally. This signal is asserted (pulled low) by the SC453

whenever the core voltage is within ±14% of the VID

programmed value. If the chip is disabled or enabled in

UVLO, then PG# is de-asserted. During start-up PG# re-

mains de-asserted until the core voltage has reached the

defined boot voltage and remains there for the BOOT pe-

riod (10μS minimum). This signal is forced low (asserted)

during VID and sleep transitions.

PG_DEL Output

This signal is delayed a minimum of 3mS from first as-

sertion of the PG# signal. This is an open drain output

and should be pulled up externally. This signal is asserted

(open drain) by the SC453 whenever the core is within

±14% of the VID programmed value. If the chip is disabled

or enabled in UVLO, then PG_DEL is de-asserted. The sig-

nal is forced high (open drain) during VID and sleep transi-

tions.

Start-Up and Sequencing

On start-up, V

BOOTV pin irrespective of the status of the VID pins. After

a minimum of 10μs, PG# asserts, and V

the VID inputs. The controller will then count 1007 switch-

ing cycles before asserting PG_DEL.

Summary of Fault Conditions

Driver Timing Diagram

CMP

BG

TG

CMPRF

tf

tpdl

tpdh

tr

tpdl

tf

tspd

tr

TG

TG

TG

BG

BG

BG

BG

tpdh

TG

(4)

(4)

Note (4): subtract a typical value of 17ns for the core comparator delay since this parameter is specified from a CMP edge.

Protection Mode

Latched?

When Active

Driver Status

SS Pin Status

Supply UVLO (VCCA, V5)

No

Always

All low

Low

32 Cycle Current Limit

Yes

SS has terminated and PGDEL is low

TG low

Sawtooth

114% V

Yes

SS has terminated and PGDEL is low

BG high

High

2.0V

Yes

Always

BG high

High

Thermal Shutdown

Yes

Always

BG, TG low

High

REFIN