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 2005 Semtech Corp.

www.semtech.com

PRELIMINARY

POWER MANAGEMENT

SC2434

Applications Information (Cont.)

The typical phase node voltage and the output voltage ripple waveform is shown in Fig. 11 under 60A full load

operation, where one can see the output ripple is very small and even with a frequency three times of the switching

frequency.

Fig. 11 - The typical phase node voltage and the output voltage ripple waveform under 60A full load operation.

The typical gate waveform for the top and bottom MOSFETs is also shown here, well-controlled dead time is

demonstrated which ensures high efficiency operation of the VR.

Fig. 12 - The typical gate waveform for the top and bottom MOSFETs.

Ch2: HS Gate

Ch3: Phase Node

Ch4: LS Gate