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Spiegazioni elettronici  Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers
PDF  49 Pages
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PCAL6408A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 18 September 2013
7 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
6.
Voltage translation
Table 4 shows how to set up VDD levels for the necessary voltage translation between the
I2C-bus and the PCAL6408A.
7.
Functional description
Refer to Figure 1 “Block diagram (positive logic)”.
7.1 Device address
The address of the PCAL6408A is shown in Figure 7.
ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW
(logic 0) to assign one of the two possible slave addresses. The last bit of the slave
address defines the operation (read or write) to be performed. A HIGH (logic 1) selects a
read operation, while a LOW (logic 0) selects a write operation.
Table 4.
Voltage translation
VDD(I2C-bus) (SDA and SCL of I2C master)
VDD(P) (Port P)
1.8V
1.8V
1.8V
2.5V
1.8V
3.3V
1.8V
5V
2.5V
1.8V
2.5V
2.5V
2.5V
3.3V
2.5V
5V
3.3V
1.8V
3.3V
2.5V
3.3V
3.3V
3.3V
5V
5V
1.8V
5V
2.5V
5V
3.3V
5V
5V
Fig 7.
PCAL6408A address
R/W
002aaf539
0
1
0
0
0
0
AD
DR
fixed
slave address
programmable



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