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TIMING INFORMATION

D

OUT

1.4V

TestPoint

3kW

100pF

C

LOAD

LoadCircuitfort

,t ,andt

dDO

r

f

VoltageWaveformsforD

RiseandFallTimes,t ,t

OUT

r

f

VoltageWaveformsforD

DelayTimes,t

OUT

dDO

VoltageWaveformsfort

dis

VoltageWaveformsfort

en

LoadCircuitfort

andt

dis

en

t

r

D

OUT

90%

10%

t

f

D

OUT

TestPoint

t

Waveform2,t

dis

en

V

DD

t

Waveform1

dis

100pF

C

LOAD

3kW

t

dis

CS

/SHDN

D

OUT

Waveform1

(3)

D

OUT

Waveform2

(4)

90%

10%

90%

4

1

B15

5

t

en

CS

/SHDN

DCLOCK

D

OUT

t

dDO

D

OUT

DCLOCK

t

hDO

(3)Waveform1isforanoutputwithinternalconditionssuchthat

theoutputishighunlessdisabledbytheoutputcontrol.

(4)Waveform2isforanoutputwithinternalconditionssuchthat

theoutputislowunlessdisabledbytheoutputcontrol.

CS/SHDN

D

OUT

DCLOCK

t

CYC

PowerDown

Conversion

Sample

Usepositiveclockedgefordatatransfer

t

SUCS

t

CONV

t

SMPL

NOTE:(1)Aminimumof22clockcyclesarerequiredfor16-bitconversion;24clockcyclesareshown.

If

remainslowattheendofconversion,anewdatastreamisshiftedoutwithLSB-firstdatafollowedbyzeroesindefinitely.

CS

B15

(MSB)

B14 B13 B12 B11 B10 B9

B8

B0

(1)

(LSB)

B7

B1

B6

B2

B5

B3

B4

Hi-Z

0

Hi-Z

t

CSD

NOTES:

CS/SHDN

D

OUT

DCLOCK

t

CONV

t

SUCS

t

CSD

t

CYC

PowerDown

t

SMPL

NOTE:(2)Aftercompletingthedatatransfer,iffurtherclocksareappliedwith

low,theA/Dconverterwilloutputzeroesindefinitely.

CS

B15

(MSB)

B14 B13 B12 B11 B6

B5

B4

B4

B3

B3

B2

B2

B1

B1

B0

Null

Bit

Hi-Z

Hi-Z

B5

B0

B11 B12 B13 B14 B15

(2)

(LSB)

(MSB)

ADS8317

SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

Figure 1. Timing Diagrams

8

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