GL9701 datasheet(39/75 Pages) GENESYS

39 / 75 page

GL9701 PCI Express

TM to PCI Bridge

Page 39

6.12 Offset 18h: Primary Bus Number Register

Bits

Type

Default

Description

7:0

00h

Primary Bus Number: Used to record the Bus Number of the

logical PCI bus segment to which the primary interface of the

bridge is connected. Configuration software is required to program

the value into this register..

6.13 Offset 19h: Secondary Bus Number Register

Bits

Type

Default

Description

7:0

00h

Secondary Bus Number: Used to record the Bus Number of the

PCI bus segment to which the secondary interface of the bridge is

connected. Configuration software programs the value in this

6.14 Offset 1ah: Subordinate Bus Number Register

Bits

Type

Default

Description

7:0

00h

Subordinate Bus Number: Used to record the Bus Number of the

highest numbered PCI bus segment which is downstream of (or

subordinate to) the bridge. Configuration software programs the

value in this register.

6.15 Offset 1bh: Secondary Latency Timer Register

Bits

Type

Default

Description

7:0

00h

Secondary Latency Timer: This register specifies, in units of PCI

bus clocks, the value of the Latency Timer for the secondary

interface GL9701.

6.16 Offset 1ch: IO Base and IO Limit Register

Bits

Type

Default

Description

3:0

I/O Base Addressing Capability: Each of these bits is hard-wired

GL9701 Scheda tecnica(PDF) 39 Page - GENESYS LOGIC

GL9701 Scheda tecnica(HTML) 39 Page - GENESYS LOGIC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

Scheda tecnica Scarica

Link URL