HYB18T512400AF datasheet(7/58 Pages) QIMONDA

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Internet Data Sheet

Rev. 1.71, 2007-01

03062006-CPCN-4867

HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]

512-Mbit DDR2 SDRAM

Pin Configuration

This chapter contains the pin configuration.

2.1

Pin Configuration for TFBGA–60 TFBGA–84

The pin configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Pin# and Buffer Type

columns are explained in Table 7 and Table 8 respectively. The pin numbering for the FBGA package is depicted in Figure 1

for

× 4, Figure 2 for × 8 and Figure 3 for × 16.

TABLE 6

Pin Configuration of DDR2 SDRAM

Pin#

Name

Type

Buffer

Type

Function

Clock Signals

×4/×8 organization

SSTL

Clock Signal CK, Complementary Clock Signal CK

SSTL

CKE

SSTL

Clock Enable

Clock Signals

×16 organization

SSTL

Clock Signal CK, Complementary Clock Signal CK

Note: See functional description in x4/x8 organization

SSTL

CKE

SSTL

Clock Enable

Note: See functional description in x4/x8 organization

Control Signals

×4/×8 organizations

RAS

SSTL

Row Address Strobe (RAS), Column Address Strobe (CAS), Write

Enable (WE)

CAS

SSTL

Chip Select

Control Signals

×16 organization

RAS

SSTL

Row Address Strobe (RAS), Column Address Strobe (CAS), Write

Enable (WE)

CAS

SSTL

Chip Select

Address Signals

×4/×8 organizations

BA0

SSTL

Bank Address Bus 1:0

BA1

SSTL

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