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HYS64D32301HU Scheda tecnica(PDF) 5 Page - Qimonda AG |
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HYS64D32301HU Scheda tecnica(HTML) 5 Page - Qimonda AG |
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5 / 39 page ![]() Internet Data Sheet Rev. 1.21, 2006-09 5 03292006-RA8T-MSZL HYS[64/72]D[16/32/128]3xxHU–[5/6]–C Unbuffered DDR SDRAM Modules 2 Pin Configuration The pin configuration of the Unbuffered DDR SDRAM DIMM is listed by function in Table 3 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 4 and Table 5 respectively. The pin numbering is depicted in Figure 1. TABLE 3 Pin Configuration of UDIMM Pin# Name Pin Type Buffer Type Function Clock Signals 137 CK0 I SSTL Clock Signals 2:0 NC NC – 16 CK1 I SSTL 76 CK2 I SSTL 138 CK0 I SSTL Complement Clock Signals 2:0 NC NC – 17 CK1 I SSTL 75 CK2 I SSTL 21 CKE0 I SSTL Clock Enable Rank 0 111 CKE1 I SSTL Clock Enable Rank 1 Note: 2-rank module NC NC – Note: 1-rank module Control Signals 157 S0 I SSTL Chip Select Rank 0 158 S1 I SSTL Chip Select Rank 1 Note: 2-rank module NC NC – Note: 1-rank module 154 RAS I SSTL Row Address Strobe 65 CAS I SSTL Column Address Strobe 63 WE I SSTL Write Enable Address Signals 59 BA0 I SSTL Bank Address Bus 2:0 52 BA1 I SSTL |
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