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Die Size (Unsawn)

1200 x 1350

47 x 53

µm

mils

Minimum Bond Pad Size

106 x 106

4.17 x 4.17

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

High Speed CMOS Logic – 54HC03

Quad 2-Input Open Drain NAND Gate in bare die form

Output Drive Capability: 10 LSTTL Loads

Low Input Current: 1µA

Outputs directly interface CMOS, NMOS and TTL

Operating Voltage Range: 2V to 6V

CMOS High Noise Immunity

Function compatible with 54LS03

Full Military Temperature Range.

Rev 1.0

16/04/18

Features:

Ordering Information

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 350µm(14 Mils) – On request

Assembled into Ceramic Package – On request

The 54HC03 is fabricated using a 2.5µm 5V CMOS process

and has the same high speed performance of LSTTL

combined with CMOS low power consumption. This device

is comprised of 3 stages including buffer output, which

enables high noise immunity with stable output. With an

external pull-up resistor the device can be used in wired

AND configuration. This device can be also used as an LED

driver and in any other application requiring a current sink.

All inputs are protected from damage due to static

discharge by internal diode clamps to VCC and Ground.

Description

Die Dimensions in µm (mils)

1200 (47)