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PJSMDA15 Scheda tecnica(PDF) 1 Page - Pan Jit International Inc. |
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PJSMDA15 Scheda tecnica(HTML) 1 Page - Pan Jit International Inc. |
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1 / 4 page ![]() PJSMDA05,05C SERIES QUAD TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION SPECIFICATION FEATURES APPLICATIONS MAXIMUM RATINGS (Per Device) Rating Symbol Value Units This Quad TVS/Zener Array family have been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up events in CMOS circuitry operating at 5V, 12V, 15V and 24V for Unidirectional and Bi-directional protection options. This TVS array offers an integrated solution to protect up to 4 data lines where the board space is a premium. 350W Power Dissipation (8/20µs Waveform) Low Leakage Current, Maximum of 5µA at rated voltage IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance Very Low Clamping Voltage RS-232C or RS-422 Communication ports GPIB/IEEE 485 Ports Portable Instrumentation ELECTRICAL CHARACTERISTICS (Per Device) Parameter Symbol Min Units Conditions Typical Max Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20µs) Clamping Voltage (8/20µs) Off State Junction Capacitance* Off State Junction Capacitance* VWRM V BR I R c V Vc Cj Cj BR I = R V = I = pp I = pp 0 Vdc Bias f = 1MHz 5V 6V µA 5 9.5 V 13 V 200 pF pF 110 1mA 5V 5A 24A 350 >25 -50 to +125 -50 to +150 W kV °C °C Peak Pulse Power (8/20µs Waveform) ESD Voltage (HBM) Per MIL-STD-883C Operating Temperature Range P pp V ESD TJ Tstg 1/23/2006 Page 1 www.panjit.com PJSMDA05, 05C Storage Temperature Range Packaged in the Industry Standard SOIC-8 1 4 5 8 1 4 5 8 Unidirectional and Bi-directional Protection Options PJSMDA05 Series PJSMDA05C Series *Note: Off-state capacitance in the bi-directional version is half of the value shown for the unidirectional. 5 Vdc Bias f = 1MHz Tj = 25°C 100% Tin Matte Finish (RoHS Compliant) |
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