MU9C8328A Ethernet Interface

Rev. 0.8 Draft

13

Processor Interface Write Cycle

Clock Timing

NOTES

1.

-1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for input-only lines (Figure 7).

2.

If this timing parameter is violated, the read or write cycle will start one SYSCLK later (assuming /AS or /CS is held).

3.

Before first network data pulse.

4.

From the SYSCLK that strobed the last DA or SA segment into the LANCAM.

5.

LANCAM Controls include /W, /CM, and /EC.

6.

See the LANCAM Handbook for additional information on LANCAM Timing Specs.

7.

With load specified in Figure 5.

8.

With load specified in Figure 6.

9.

Pin A(3)

SYSCLK

SERCLK

1

2

3

45

7

6

8

SYSCLK

/CS

/AS

A(2-0)

/WE

D(15-0)

READY

9

9

12

13

14

17

18

19

20

16

10

10

11

11

15

21