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STW81101ATR Scheda tecnica(PDF) 33 Page - STMicroelectronics |
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STW81101ATR Scheda tecnica(HTML) 33 Page - STMicroelectronics |
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33 / 48 page ![]() STW81101 SPI digital interface 33/48 7 SPI digital interface 7.1 General features The SPI digital interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 3.3V. The STW81101 IC is programmed by means of a high-speed serial-to-parallel interface with write option only. The 3-wire bus can be clocked at a frequency as high as 100MHz to allow fast programming of the registers containing the data for RF IC configuration. The chip is programmed through serial words with a full length of 26 bits. The first 2 MSBs represent the address of the registers, and the 24 LSBs represent the value of the registers. Each data bit is stored in the internal shift register on the rising edge of the CLOCK signal. The outputs of the selected register are sent to the device on the rising edge of the LOAD signal. Figure 26. SPI input and output bit order Last bit sent (LSB)0 2 23 24 25(MSB) A1 LOAD #4 Address decoder 1 DATA LOAD Reg.#4 Reg.#1 Reg.#0 D23 (MSB) D0 (LSB) |
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