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FXLS8971CF Scheda tecnica(PDF) 64 Page - NXP Semiconductors |
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FXLS8971CF Scheda tecnica(HTML) 64 Page - NXP Semiconductors |
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64 / 100 page ![]() NXP Semiconductors FXLS8971CF 3-Axis Low-g Accelerometer Field Description 0 BAFRO Back or front orientation 0: Front: The device is in the front-facing orientation. 1: Back: The device is in the back-facing orientation. Note: The BAFRO bit continues to update with orientation changes even after the NEW_ORIENT flag is set. Table 83. ORIENT_STATUS register (address 28h) bit description...continued Notes: • The BAFRO and LAPO fields are reset to 0 after a POR or soft reset event. These bits are also automatically cleared after a transition from STANDBY to ACTIVE or STANDBY to EXT_TRIG modes. • The current orientation is locked if the absolute value of the acceleration experienced on any of the three axes is greater than 1.25 g. 15.4.2 ORIENT_CONFIG register (address 29h) This register is used to enable the orientation detection function and set the behavior of the orientation transition debounce counter. Bit 7 6 5 4 3 2 1 0 Name ORIENT_ DBCNTM ORIENT_ ENABLE — Reset 1 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 84. ORIENT_CONFIG register (address 29h) bit allocation Field Description 7 ORIENT_DBCNTM Orientation debounce counter mode selection 0: Orientation debounce counter is decremented whenever the current orientation is different than the previous one. 1: Orientation debounce counter is cleared whenever the current orientation is different than the previous one. 6 ORIENT_ENABLE Orientation detection function enable 0 (default): Orientation detection function is disabled. 1: Orientation detection function is enabled. Table 85. ORIENT_CONFIG register (address 29h) bit description 15.4.3 ORIENT_DBCOUNT register (address 2Ah) The ORIENT_DBCOUNT register sets the debounce count used for validating an orientation state change. The selected ODR in LPM and HPM modes, and the effective ODR when operating in FPM determine the debounce counter period. Calculate the minimum debounce latency time by ODR–1 * ORIENT_DBCOUNT[7:0]. For example, with an ODR of 100 Hz and debounce count value of 10, the new orientation must be maintained for 100 ms before it is recognized as a valid orientation and ORIENT_STATUS[NEW_ORIENT] is asserted. A transition from Standby to Active, a transition from Active to Standby, or a change in the auto-WAKE/SLEEP mode resets the internal orientation debounce counter. FXLS8971CF All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 2.1 — 7 March 2024 64 / 100 |
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