PCI 9656

64-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola

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Maximum PCI Bandwidth for Your 32-bit Local Bus Applications

The PCI 9656 offers flexible connectivity and high performance I/O acceleration features

to enable leading edge PCI, CompactPCI, and embedded host designs.

The PCI 9656 is the perfect match for the industry leading 32-bit communication proces-

sor, the Motorola MPC 850/860 PowerQUICC. The PCI 9656 provides a direct connection

to PowerQUICC devices, enabling high-speed 64-bit, 66MHz PCI performance with its

Data Pipe Architecture™ technology.

Generic 32-bit, 66MHz Local Bus Designs

The PCI 9656 provides direct connection to two generic industry standard interconnect

buses. Designers use these 32-bit, 66MHz buses for a myriad of high-speed devices rang-

ing from processors, to DSPs, to memories, to custom ASICs and FPGAs.

The PCI 9656 Data Pipe Architecture technology enables high-speed, 64-bit, 66MHz PCI

I/O with those devices.

Move Your 32-bit Local Bus Designs Up to

64-bit, 66MHz PCI Operation

As PCI evolves to meet the ever increasing I/O demands of leading edge systems, PLX

continues to provide leading edge, high performance PCI I/O acceleration solutions. Based

on the architecture of the industry-leading PCI 9054, the PCI 9656 offers a variety of

enhancements for the needs of today's telecom, networking, and I/O adapter designs:

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64-bit, 66MHz PCI operation

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32-bit, 66MHz local bus operation

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Dynamic DMA descriptor ring management with Valid bit semaphore control

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PICMG 2.1 r2.0 Hot Swap Silicon, including Bias Voltage, Early Power, 64-bit

Initialization, and Intially Not Responding Support

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PCI arbiter supporting 7 external masters

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Reset and interrupt pins configurable for embedded host applications

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JTAG boundary scan

The PCI 9656 is register compatible with the PCI 9054, enabling easy software migration.

Connectivity

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64-bit, 66MHz PCI r2.2 compliant

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Motorola PowerQUICC and

generic 32-bit, 66MHz local

bus modes

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3.3V I/O, 5V tolerant bus

interfaces

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PICMG 2.1 r2.0 Hot Swap Silicon

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272-ball, 27 x 27 mm, 1.27 mm

pitch PBGA

Performance

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Zero wait state burst operation

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2 DMA Channels

Hardware controls

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Direct Master data transfers

read prefetch counter

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Direct Slave data transfers

bus devices

read ahead, posted writes, pro-

grammable read prefetch counter

Control

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I2O r1.5 messaging unit

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Eight mailbox and two

doorbell registers

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PCI arbiter supports 7

external masters

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Host mode reset/interrupt signal

configuration

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Event (PME) generation support

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Serial EEPROM interface

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JTAG boundary scan

VERSION

1.0

2002