74LVC2G74_3

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 — 9 August 2007

10 of 19

NXP Semiconductors

74LVC2G74

Single D-type flip-flop with set and reset; positive edge trigger

12. Waveforms

Measurement points are given in Table 10.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 7.

The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the

CP to D hold times and the CP maximum frequency

mnb141

GND

GND

CP input

D input

Q output

Q output

Table 10.

Measurement points

Supply voltage

Input

Output

1.65 V to 1.95 V

0.5

0.5

2.3 V to 2.7 V

0.5

0.5

2.7 V

1.5 V

1.5 V

3.0 V to 3.6 V

1.5 V

1.5 V

4.5 V to 5.5 V

0.5

0.5