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TMPR4937 Scheda tecnica(PDF) 63 Page - Toshiba Semiconductor |
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TMPR4937 Scheda tecnica(HTML) 63 Page - Toshiba Semiconductor |
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63 / 552 page ![]() Chapter 3 Signals 3-9 3.1.13 Initialization Signal Table 3.1.13 Initialization Signal Signal Name Type Description Initial State RESET* Input Reset Reset signal. Input 3.1.14 Test Signals Table 3.1.14 Test Signals Signal Name Type Description Initial State TEST[4:0]* Input PU Test Mode Setting Test pins. These pins must be left open or fixed to High. TEST[1]* may be used when debugging the system. Toshiba recommends that your board design enable the pin to be driven low after the TX4937 is mounted on the PC board. Contact Toshiba technical staff for more information on the TEST[1]* functions. Input 3.1.15 Power Supply Pins Table 3.1.15 Power Supply Pins Signal Name Type Description Initial State PLL1VDD_A, PLL2VDD_A ⎯ PLL Power Pins PLL analog power supply pins. PLL1VDD_A = 1.5 V. PLL2VDD_A = 1.5 V. ⎯ PLL1VSS_A, PLL2VSS_A ⎯ PLL Ground Pins PLL analog ground pins. PLL1VSS_A = 0 V. PLL2VSS_A = 0 V. ⎯ VccInt ⎯ Internal Power Pins Digital power supply pins for internal logic. VccInt = 1.5 V. ⎯ VccIO ⎯ I/O Power Pins Digital power supply pins for input/output pins. VccIO = 3.3 V. ⎯ Vss ⎯ Ground Pins Digital ground pins. Vss = 0 V. ⎯ |
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