TMPR4937 datasheet(177/552 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-21

8.3.12 Interrupts

An interrupt number (10 – 13) of the Interrupt Controller is mapped to each channel. In addition,

there are completion interrupts for when transfer ends normally and error interrupts for when transfer

ends abnormally for each channel. When an interrupt occurs, then the bit that corresponds to either the

Normal Interrupt Status field (DIS[3:0]) or the Error Interrupt Status field (EIS[3:0]) of the DMA

Master Control Register (DMMCR) is set.

Figure 8.3.6 shows the relationship between the Status bit and Interrupt Enable bit for each interrupt

cause. Refer to the explanation for each Status bit for more information regarding each information

cause.

Figure 8.3.6 DMA Controller Interrupt Signal

8.3.13 Transfer Stall Detection Function

If the period from when a certain channel last performs internal bus access to when the next internal

bus access is performed exceeds the Transfer Stall Detection Interval field (STLTIME) of the DMA

Channel Control Register (DMCCRn), the Transfer Stall Detection bit (STLXFER) of the DMA

Channel Status Register (DMCSRn) is set. An error interrupt is signalled if the Error Interrupt Enable

bit (DMCCRn.INTENE) is set.

In contrast to other error interrupts, DMA transfer is not stopped. Normal DMA transfer is executed if

bus ownership can be obtained. Furthermore, clearing the Transfer Stall Detection field (STLXFER)

resumes transfer stall detection as well.

Setting the Transfer Stall Detection Interval field (STLTIME) to “000” disables the Transfer Stall

Detection function.

DMMCR.DIS[n]

DMCSRn.CFERR

DMCSRn.CHERR

DMCSRn.DESERR

DMCSRn.SORERR

DMCSRn.STLXFER

DMMCR.EIS[n]

DMCCRn.INTENE

DMCSRn.NCHNC

DMCCRn.INTENC

DMCSRn.NTRNFC

DMCCRn.INTENT

Interrupt Controller

(Interrupt No. 10 – 13)

DMCSRn.ABCHC

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