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TMP86FS23UG Scheda tecnica(PDF) 65 Page - Toshiba Semiconductor |
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TMP86FS23UG Scheda tecnica(HTML) 65 Page - Toshiba Semiconductor |
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65 / 252 page ![]() Page 53 TMP86FS23UG Figure 5-2 Port P1 Note: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction. P1DR (0001H) R/W 76 543 21 0 P17 SEG24 P16 SEG25 P15 SEG26 P14 SEG27 INT3 P13 SEG28 INT2 P12 SEG29 INT1 P11 SEG30 TXD P10 SEG31 RXD BOOT (Initial value: 0000 0000) P1LCR (0F9EH) 76 543 21 0 (Initial value: 0000 0000) P1LCR Port P1/segment output control (set for each bit individually) 0: P1 input/output port or secondary function (expect for segment) 1: LCD segment output R/W P1CR (0009H) 76 543 21 0 (Initial value: 0000 0000) P1CR P1 port input/output control (set for each bit individually) 0: Input mode 1: Output mode R/W P1LCRi Output latch Data output (P1DRi) LCD data output Control output STOP OUTEN P1LCRi input P1CRi P1CRi input Data input (P1DRi) Control input P1i Note:i=7 to 0 DQ DQ DQ |
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