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KSZ9567R Scheda tecnica(PDF) 118 Page - Microchip Technology |
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KSZ9567R Scheda tecnica(HTML) 118 Page - Microchip Technology |
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118 / 233 page ![]() KSZ9567R DS00002329E-page 118 2022 Microchip Technology Inc. and its subsidiaries 8 Enable Checking of Associated Delay_Req and Delay Resp PTP Messages Setting this bit will associate Delay_Resp message with Delay_Req message when it has the same domain, sequenceID and sourcePortID. The PTP frame will be forwarded to the host port if the ID matches. R/W 0b 7 Enable Checking of Associated Pdelay_Req and Pdelay_Resp PTP Messages Setting this bit will associate Pdelay_Resp/Pdelay_Resp_Follow_Up message with Pdelay_Req message when it is with the same domain, sequenceID and sourcePortID. The PTP frame will be forwarded to the host port if ID matches. R/W 0b 6 RESERVED R/W 0b 5 Enable Dropping of Sync/Follow_Up and Delay_Req PTP Messages Setting this bit will enable the device to automatically drop these Sync/ Follow_up and Delay_Req PTP messages if the Best Master Clock (BMC) is not determined. R/W 0b 4 Enable Checking of Domain Field Setting this bit will enable the device to automatically check the domain field of the PTP message with the PTP_DOMAIN in the Global PTP Domain and Version Register. The PTP message will be forwarded to the host port if the domain field matches. Otherwise it will be dropped. R/W 0b 3 RESERVED R/W 0b 2 Enable IPv4/UDP Checksum Calculation for Egress Packets 1 = The switch will re-calculate and generate a 2-byte checksum value when the frame content changes. 0 = The checksum field is set to zero. If the IPv4/UDP checksum is zero, the checksum will remain zero regardless of this bit setting. For IPv6/UDP, the checksum is always updated. R/W 1b 1 RESERVED R/W 0b 0 RESERVED R/W 0b Bits Description Type Default |
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