M58BW016DB datasheet(19/69 Pages) STMICROELECTRONICS

19 / 69 page

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Bus operations

19/69

3.1.3

Asynchronous Page Read

Asynchronous Page Read operations are used to read from several addresses within the

same memory page. Each memory page is 4 double-words and is addressed by the

address inputs A0 and A1.

Data is read internally and stored in the page buffer. Valid bus operations are the same as

Asynchronous Bus Read operations but with different timings. The first read operation within

the page has identical timings, subsequent reads within the same page have much shorter

access times. If the page changes then the normal, longer timings apply again. Page Read

does not support Latched Controlled Read.

See Figure 10: Asynchronous Page Read AC waveforms, and Table 18: Asynchronous

Page Read AC characteristics, for details on when the outputs become valid.

3.1.4

Asynchronous Bus Write

Asynchronous Bus Write operations write to the command interface to send commands to

the memory or to latch addresses and input data to program. Bus Write operations are

asynchronous, the clock, K, is Don’t care during Bus Write operations.

A valid Asynchronous Bus Write operation begins by setting the desired address on the

address inputs, and setting Chip Enable, Write Enable and Latch Enable Low, VIL, and

Output Enable High, VIH, or Output Disable Low, VIL. The address inputs are latched by the

command interface on the rising edge of Chip Enable or Write Enable, whichever occurs

first. Commands and input data are latched on the rising edge of Chip Enable, E, or Write

Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable

Low, during the whole Asynchronous Bus Write operation.

See Figure 11: Asynchronous Write AC waveforms, and Table 19: Asynchronous Write and

Latch Controlled Write AC characteristics, for details of the timing requirements.

3.1.5

Asynchronous Latch Controlled Bus Write

Asynchronous Latch Controlled Bus Write operations write to the command interface to

send commands to the memory or to latch addresses and input data to program. Bus Write

operations are asynchronous, the clock, K, is Don’t care during Bus Write operations.

A valid Asynchronous Latch Controlled Bus Write operation begins by setting the desired

address on the address inputs and pulsing Latch Enable Low, VIL. The address inputs are

latched by the command interface on the rising edge of Latch Enable, Write Enable or Chip

Enable, whichever occurs first. Commands and input data are latched on the rising edge of

Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain

High, and Output Disable Low, during the whole Asynchronous Bus Write operation.

See Figure 12: Asynchronous Latch Controlled Write AC waveforms, and Table 19:

Asynchronous Write and Latch Controlled Write AC characteristics, for details of the timing

requirements.

3.1.6

Output Disable

The data outputs are high impedance when the Output Enable, G, is at VIH or Output

Disable, GD, is at VIL.

M58BW016DB Scheda tecnica(PDF) 19 Page - STMicroelectronics

M58BW016DB Scheda tecnica(HTML) 19 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

Scheda tecnica Scarica

Link URL