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DF2S8.2FS Scheda tecnica(PDF) 2 Page - Toshiba Semiconductor |
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DF2S8.2FS Scheda tecnica(HTML) 2 Page - Toshiba Semiconductor |
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2 / 3 page ![]() DF2S8.2FS 2007-11-01 2 Guaranteed Level of Esd Immunity Marking Equivalent Circuit (Top View) 7 Criterion: No damage to device elements Test Condition ESD Immunity Level IEC61000-4-2 (Contact discharge) ±30kV IZ - VZ 0 0 0 1 10 100 2345 67 89 10 11 12 0.01 Ta=25°C 0.1 0.001 ZENER VOLTAGE VZ (V) CT - VR 1 10 100 012 3 4567 f=1MHz Ta=25°C REVERSE VOLTAGE VR(V) |
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