Preliminary Technical Data

ADIS16209

Rev. PrA | Page 7 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AUX DAC

NC

NC

RST

SCLK

DOUT

DIN

CS

ADIS16209

TOP

LOOK THROUGH

VIEW

(Not to Scale)

16

15

14

13

5

6

7

8

PIN 1

INDICATOR

NOTES

1. NC = NO CONNECT

2. THIS IS NOT AN ACTUAL “TOP VIEW,” AS THE PINS ARE NOT VISIBLE FROM THE TOP. THIS IS A

LAYOUT VIEW, WHICH REPRESENTS THE PIN CONFIGURATION, IF THE PACKAGE IS LOOKED

THROUGH FROM THE TOP. THIS CONFIGURATION IS PROVIDED FOR PCB LAYOUT PURPOSES.

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

SCLK

I

SPI, Serial Clock.

2

DOUT

O

SPI, Data Output.

3

DIN

I

SPI, Data Input.

4

CS

I

SPI, Chip Select.

5, 6

DIO1, DIO2

I/O

Digital Input/Output Pins.

7, 8, 10, 11

NC

–

No Connect.

9

RST

I

Reset, Active Low.

12

AUX DAC

O

Auxiliary DAC Output.

13

VDD

S

Power Supply, +3.3 V.

14

AUX ADC

I

Auxiliary ADC Input.

15

VREF

O

Precision Reference.

16

GND

S

Ground.

RECOMMENDED PAD GEOMETRY

0.670

12×

1.127

16×

4.1865

8×

2.6955

8×

5.391

4×

8.373

2×

0.500

16×

9.2mm × 9.2mm STACKED LGA PACKAGE

Figure 6. Example of a Pad Layout