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TLV755P Scheda tecnica(PDF) 21 Page - Texas Instruments |
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TLV755P Scheda tecnica(HTML) 21 Page - Texas Instruments |
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21 / 49 page ![]() 7.4 Layout 7.4.1 Layout Guidelines • Place input and output capacitors as close as possible to the device. • Use copper planes for device connections to optimize thermal performance. • Place thermal vias around the device to distribute the heat. • For packages with thermal pads, solder the thermal pad to copper to achieve best thermal resistance. Thermal resistance increases significantly when the thermal pad is not soldered. 7.4.2 Layout Examples OUT IN GND PLANE Represents via used for application specific connections 1 2 3 4 C IN C OUT EN Figure 7-6. Layout Example for the DQN Package VOUT VIN GND PLANE Represents via used for application specific connections 1 2 3 4 5 C OUT C IN EN Figure 7-7. Layout Example for the DBV Package VIN VOUT GND PLANE Represents via used for application specific connections 1 2 3 4 6 C IN C OUT EN 5 Figure 7-8. Layout Example for the DRV Package www.ti.com TLV755P SBVS320D – NOVEMBER 2017 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TLV755P |
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