ADIN1101BCPZ-R7 datasheet(9/79 Pages) AD

9 / 79 page

Data Sheet

ADIN1101

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

analog.com

Rev. A | 9 of 79

Table 8. Pin Function Descriptions (Continued)

Pin No.

Mnemonic1

PU/PD2

Description

LDO and Reference Decoupling

CEXT_2

N/A

External Decoupling for LDO Circuit. Connect a 0.1 μF capacitor to ground as

close as possible to this pin. Do not use this pin as a voltage source for an

external circuit.

CEXT_3

N/A

External Decoupling for LDO Circuit. Connect a 1 μF capacitor to ground as

close as possible to this pin. Do not use this pin as a voltage source for an

external circuit.

Power and Ground Pins

AVDD_H

N/A

Analog Supply Voltage for the Various Analog Circuits in the Device. This

supply rail can be supplied by 1.8 V to 3.3 V depending on the transmit level

configuration. If AVDD_H is 3.3 V, both 1.0 V p-p and 2.4 V p-p transmit

operating modes are supported. If AVDD_H is 1.8 V, only 1.0 V p-p transmit

operating mode is supported. Connect 0.1 μF and 0.01 μF capacitors to GND

as close as possible to this pin.

AVDD_L

N/A

Analog Supply Voltage for the Internal LDO Circuits. This supply rail can be

supplied by 1.8 V to 3.3 V. AVDD_L can be connected directly to the AVDD_H

rail in long reach applications or alternatively to the VDDIO rail when the device

is configured with dual supplies for lower power consumption. Connect 0.1 μF

and 0.01 μF capacitors to GND as close as possible to this pin.

DLDO_1P1

N/A

Output from an Internal 1.1 V LDO Circuit. Connect a 0.68 μF capacitor to

ground as close as possible to this pin.

VDDIO

N/A

3.3 V, 2.5 V, or 1.8 V Digital Power for MDIO and MAC Interface. Connect 0.1

μF and 0.01 μF capacitors to GND as close as possible to the pin.

EP (GND)

N/A

Exposed Pad (Ground). This GND paddle must be connected to ground. The

LFCSP package has an exposed pad that needs to be connected to GND

for electrical reasons and must be soldered to a metal plate on the PCB for

mechanical reasons. A 4 × 4 array of thermal vias beneath the exposed GND

pad is also recommended.

Other Pins

9, 10

N/A

No Connect.

1 Where a pin is shared between a functional signal and a hardware configuration pin signal, the hardware configuration pin signal is listed last.

2 PU/PD refers to internal/on-chip pull-up or pull-down resistors. All of the hardware configuration pins have internal pull-down resistors. The default mode of operation

without any external resistors connected to these pins is shown in Table 14. If an alternative mode of operation is required, use 4.7 kΩ pull-up resistors. N/A means not

applicable.

ADIN1101BCPZ-R7 Scheda tecnica(PDF) 9 Page - Analog Devices

ADIN1101BCPZ-R7 Scheda tecnica(HTML) 9 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Scheda tecnica Scarica

Link URL