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Support for per-core CoreSight ELA-600 to monitor the hardware signals within the

core. The configuration option to pre-integrate ELAs is global. (Note the CoreSight

ELA-600 is a separately licensable product.)

A cluster level PMU to monitor events that happen at the shared logic. Provides six

performance event counters and one cycle counter.

AMBA 4 APB interfaces between the cluster and the DebugBlock.

DebugBlock

The DebugBlock transfers trigger events to/from the Cortex-R82 processor.

The DebugBlock is separated from the Cortex-R82 processor to facilitate the following

system design options:

The DebugBlock is placed in a separate power domain, to ensure that it is possible

to maintain the connection to a debugger while the cores and cluster are

powered down.

The DebugBlock is physically placed with the other CoreSight logic in the SoC, rather

than close to the cluster.

The separate power domains allow the cores and the cluster to be powered down while

maintaining essential state that is required to continue debugging. Separating the logical

power domains into physical domains is optional and might not be available in individual

systems.

System debug APB

The system debug APB slave interface connects to external CoreSight components, such as

the Debug Access Port (DAP) to provide access to the Debug registers, ETM, and ELA in each

core within the Cortex-R82 processor.

CTI and CTM

The DebugBlock implements Embedded Cross Trigger (ECT). A Cross Trigger Interface (CTI)

is allocated to each core in the cluster. An additional CTI is allocated to the cluster PMU and,

if present, to the cluster ELA. The CTIs are interconnected through the Cross Trigger Matrix

(CTM). A single external channel interface is implemented to allow cross-triggering to be

extended to the SoC.