6

AX11025

Single Chip Microcontroller with TCP/IP

and 10/100M Fast Ethernet MAC/PHY

Features

Product Brief

MCU

8-bit

pipelined

RISC,

single

cycle

per

instruction

with

maximum

operating

frequency of 100Mhz (100 MIPS)

100% software compatible with standard

8051/80390

4 GPIO ports of 8 bits each

2 external interrupt sources with 2 priority

levels

Support

power

management

unit,

programmable watchdog timer, and 3 16-bit

timer/counters

Debug port for connecting to In-Circuit

Emulation (ICE) adaptor

5 channels of Programmable Counter Array

(PCA)

On-chip Program and Data Memory

Embed 512KB Flash memory, and 16KB

SRAM for program code mirroring. The

external program memory can grow up to

2MB without bank select

Support initial Flash memory programming

via UART or ICE adaptor, the so-called In

System Programming (ISP)

Support run-time firmware or driver update

through Ethernet or UART, the so-called In

Application Programming (IAP)

Support boot loader to shadow program code

on to internal 16KB SRAM and external

SRAM for high performance applications

Embed 32KB SRAM for data memory,

expandable up to 2MB via external SRAM

without bank select

Buffer Management

Innovative shared memory architecture to

allow external program and data memory to

share the same SRAM memory chip with

flexible memory space allocation

Embed DMA engine and memory arbiter.

Support

3

DMA

channels

for

high

performance

data

movement

needed

for

network protocol stack processing

On-chip 10/100M Fast Ethernet MAC and PHY

Integrate IEEE 802.3 10BASE-T/100BASE-TX

compatible Fast Ethernet MAC and PHY with

dedicated 12KB SRAM for Ethernet packet

buffering. Support full-duplex and half-duplex

operations. Provide optional MII interface (for

HomePNA and HomePlug)

Support twisted pair crossover detection and

auto-correction (HP Auto-MDIX)

Support wakeup via Link-up, Magic packet,

Wakeup frame or external input pin

TCP/IP

Build in TCP/IP accelerator in hardware to

improve network transfer throughput. Support

IP/TCP/UDP/ICMP/IGMP

checksum

and

ARP in hardware

Support TCP, UDP, ICMP, IGMP, IPv4,

DHCP, BOOTP, ARP, and HTTP in software

Communication Interface

3

UART

interface

(with

1

supporting

921.6Kbps and Modem control)

1 I2C interface (master and slave mode)

SPI/Micro wire interface (3 masters or 1 slave

mode)

1 1-Wire controller interface (master mode)

1 CAN 2.0 controller interface

10/100 Ethernet PHY interface

Support network boot over Ethernet using BOOTP

and TFTP

Integrate on-chip 3.3V to 1.8V voltage regulator and

require single power supply of 3.3V only

Integrate on-chip oscillator and PLL. Require only

one 25Mhz crystal to operate

Integrate on-chip power-on reset circuit

128-pin LQFP RoHS package

Operating temperature: -40 to 85°C

*IEEE is a registered trademark of the Institute of Electrical and

Electronic Engineers, Inc.

*All other trademarks and registered trademark are the property of their

respective holders.

Product Description

The AX11025, Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY, is a System-on-Chip

(SoC) solution which offers a high performance embedded micro controller and rich communication peripherals for

wide varieties of application which need access to the LAN or Internet. With built-in network protocol stack, the

AX11025 provides very cost effective networking solution to enable simple, easy, and low cost Internet connection

capability for many applications such as consumer electronics, networked home appliances, industrial equipments,

security systems, remote data collection equipments, remote control, remote monitoring, and remote management.

ASIX Electronics Corporation

4F, No.8, Hsin Ann Rd.,

Hsinchu Science Park,

Hsinchu 30078, Taiwan

ASIX Proprietary and Confidential

Released Date: 8/11/2006

TEL: +886-3-579-9500

FAX: +886-3-579-9558

http://www.asix.com.tw/