TC9256, 57APG/AFG

2006-07-14

10

Programmable Counter

The programmable counter section consists of a 1/2 prescaler, a two-modulus prescaler and a 4 bit

+ 12 bit

programmable binary counter.

1.

Setting of Programmable Counter

16 bits of divisor data and 2 bits indicating the dividing mode are set in the programmable counter.

(1)

Setting dividing mode

The FM and MODE bits are used to select the input pin and the dividing mode (pulse-swallow mode

or direct dividing mode). There are fourtypes of mode, as shown in the table below. Select one based on

the frequency band being used.

(2)

Setting divisor

The divisor for the programmable counter is set as binary data in bits P0 to P15.

Pulse-swallow mode (16 bits)

Divisor setting range (pulse-swallow mode): n

= 210H to FFFFH (528 to 65535)

Note:

In the 1/2

+ pulse-swallow mode, the actual divisor is twice the programmed value.

Direct dividing mode (12 bits)

Divisor setting range (direct dividing mode): n

= 10H to FFFH (16 to 4095)

With the direct dividing mode, data P0 to P3 are don’t-care and bit P4 is the LSB.