DSP56721 datasheet(43/54 Pages) FREESCALE

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SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

Figure 36. S/PDIF SRCK Timing Diagram

Figure 37. S/PIDF STCLK Timing Diagram

2.2.11

EMC Timing (DSP56720 only)

The DSP56721 device does not have an EMC module. For EMC timing parameters in DSP56720 devices, see Table 20,

Table 21, and Table 22; for timing diagrams, see Figure 38, Figure 39, and Figure 40.

Table 20. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2)

Parameter

Symbol

Min

Max

Unit

LCLK cycle time

Tclk

–

LCLK skew to LSYNC_OUT

Tclk_skew

–

160

Input setup to LSYNC_IN (except LGTA/LUPWAIT)

Tin_s

2–

Input hold from LSYNC_IN (except LGTA/LUPWAIT)

Tin_h

2–

LGTA valid time

Tgta

–

LUPWAIT valid time

Tupwait

–

LALE negedge to LAD(address phase) invaild (address latch

hold time)

Tale_h

3–

LALE valid time

Tale

3.8

–

Output setup from LSYNC_IN (except LAD[23:0] and LALE)

Tout_s

4–

Output hold from LSYNC_IN (except LAD[23:0] and LALE)

Tout_h

2–

LAD[23:0] output setup from LSYNC_IN

Tad_s

3.5

–

LAD[23:0] output hold from LSYNC_IN

Tad_h

1.5

–

LSYNC_IN to output high impedance for LAD[23:0]

Tad_z

–4.3

SRCK

(Output

)

srckp

srckph

srckpl

STCLK

(Input)

stclkp

stclkph

stclkpl

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