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F1953 Scheda tecnica(PDF) 12 Page - Renesas Technology Corp |
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F1953 Scheda tecnica(HTML) 12 Page - Renesas Technology Corp |
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12 / 22 page ![]() F1912 Datasheet R35DS0055EU0100 Rev.1.00 Nov 10, 2022 Page 12 Figure 3. Latched Parallel Mode Timing Diagram Table 6. Latched Parallel Mode Timing Interval Symbol Description Min Spec Max Spec Unit tsps Serial to Parallel Mode Setup Time 100 ns tpdh Parallel Data Hold Time 10 ns tpds LE minimum pulse width 10 ns tle Parallel Data Setup Time 10 ns 4. Typical Operating Conditions (TOC) Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply. ■ VDD = +3.30 V ■ TCASE = +25 °C ■ FRF = 2 GHz ■ PIN = 0 dBm for single tone measurements ■ PIN = +10 dBm/tone for multi-tone measurements ■ Tone Spacing = 50 MHz ■ EVKit connector and board losses are de-embedded |
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