General Note

TT Electronics reserves the right to make changes in product specification without

notice or liability. All information is subject to TT Electronics’ own data and is

considered accurate at time of going to print.

TT Electronics | OPTEK Technology

2900 E. Plano Parkway, St 200, Plano, TX 75074, USA | Ph: +1 972 323 2200

www.ttelectronics.com | sensors@ttelectronics.com

Rev C, 4/27/2023

Page 33

© TT electronics plc

FlexSense® I-Series Programmable

Incremental Encoder

FS210/FS310 Datasheet

Figure 11: I2C Bit Transfer

During data transfer the logic level on SDA may be changed only when a low logic level is present on SCL. (A change in SDA

logic level when SCL is high is interpreted as either a S(START) condition or a P(STOP) condition.) The “S” condition is

generated by creating a falling edge on the SDA pin while the SCL pin is at a high logic level. The “P” condition is generated

by creating a rising edge on the SDA pin while the SCL pin is at a high logic level. All I2C bus transactions must begin with a

master-generated “S” condition. All transactions should end with a master-generated “P” condition. The FS210/FS310 will

not accept a START-Repeat (Sr) condition, so all commands must have explicit Start and Stop conditions.

For data bits being transmitted to the device, the FS210/FS310 determines the bit value by sampling SDA at SCL↑. For

logic-0 data bits being transmitted by the device, the FS210/FS310 begins to drive SDA low1 immediately after SCL↓, so that

the I2C master can determine the bit value of SDA at the following SCL↑.

All data bytes are transmitted MSB-first, and all data bytes include a 9th SCL period in which the device that received the

byte acknowledges, either positively (A) or negatively (A\), to the device that transmitted the byte.

When the FS210/FS310 is acting as an I2C master – only during a power-up sequence when the MODE pin is at a high logic

level – it is expected to read data from an off-chip non-volatile memory connected to the same I2C bus. During a master-

mode power-up sequence, the device directs I2C read accesses to the off-chip non-volatile memory with a fixed device

address of 0x50. Contact the factory if an off-chip non-volatile memory with a different I2C slave address is required.

When the FS210/FS310 is acting as a slave – any time not during a power-up sequence – it comprehends two I2C

commands: Write To Slave and Read From Slave. Both command sequences begin with a start condition, followed by a 7-

bit slave address transmitted from the I2C bus master to the FlexSenseTM device:

• I2C slave address with a “Write” direction bit (SA-W).

o

The 7-bit I2C slave address assigned to the FS210/FS310 is ‘h31. The direction bit is appended at the least-

significant end of the 7-bit I2C slave address. A “Write” direction bit is encoded as 0, so the entire byte is

‘b1100010 = ‘h62.

o

Two-byte FS210/FS310 target address for the Write command, transmitted least-significant-byte-first.

o

0 or more bytes may follow. The address pointer self-increments after every successfully written byte.

• I2C slave address with a “Read” direction bit (SA-R).

o

A “Read” direction bit is encoded as 1, so the slave address would be ‘b1100011 = ‘h63

o

0 or more bytes can then be read from the FlexSenseTM device starting at the last address pointer. The

address pointer self-increments after every successfully read byte.

o

The master can signify that the reads are complete by issuing a NACK on the last desired byte, i.e. by not

acknowledging the last byte on the ninth bit.

1 To transmit a logic-1 data bit, the FS210 does not drive SDA at all – it is an open-drain pin.