DS90CP22

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SNLS053E – MARCH 2000 – REVISED APRIL 2013

Electrical Characteristics

(1)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

CMOS/TTL DC SPECIFICATIONS (EN0,EN1,SEL0,SEL1)

VIH

High Level Input Voltage

2.0

VCC

V

VIL

Low Level Input Voltage

GND

0.8

V

IIH

High Level Input Current

VIN = 3.6V or 2.0V; VCC = 3.6V

+7

+20

μA

IIL

Low Level Input Current

VIN = 0V or 0.8V; VCC = 3.6V

±1

±10

μA

VCL

Input Clamp Voltage

ICL = −18 mA

−0.8

−1.5

V

LVDS OUTPUT DC SPECIFICATIONS (OUT0,OUT1)

VOD

Differential Output Voltage

RL = 75Ω

270

365

475

mV

RL = 75Ω, VCC = 3.3V, TA = 25°C

285

365

440

mV

ΔVOD

Change in VOD between Complimentary Output States

35

mV

VOS

Offset Voltage(2)

1.0

1.2

1.45

V

ΔVOS

Change in VOS between Complimentary Output States

35

mV

IOZ

Output TRI-STATE Current

TRI-STATE Output,

±1

±10

μA

VOUT = VCC or GND

IOFF

Power-Off Leakage Current

VCC = 0V; VOUT = 3.6V or GND

±1

±10

μA

IOS

Output Short Circuit Current

VOUT+ OR VOUT− = 0V

−15

−25

mA

IOSB

Both Outputs Short Circuit Current

VOUT+ AND VOUT− = 0V

−30

−50

mA

LVDS RECEIVER DC SPECIFICATIONS (IN0,IN1)

VTH

Differential Input High Threshold

VCM = +0.05V or +1.2V or +3.25V,

0

+100

mV

VTL

Differential Input Low Threshold

Vcc = 3.3V

−100

0

mV

VCMR

Common Mode Voltage Range

VID = 100mV, Vcc = 3.3V

0.05

3.25

V

IIN

VIN = +3.0V, VCC = 3.6V or 0V

±1

±10

μA

Input Current

VIN = 0V, VCC = 3.6V or 0V

±1

±10

μA

SUPPLY CURRENT

ICCD

Total Supply Current

RL = 75Ω, CL = 5 pF, EN0 = EN1 = High

98

125

mA

ICCZ

TRI-STATE Supply Current

EN0 = EN1 = Low

43

55

mA

(1)

All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.

(2)

VOS is defined and measured on the ATE as (VOH + VOL) / 2.

AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

TSET

Input to SEL Setup Time(2), (Figure 3 and Figure 4)

0.7

0.5

ns

THOLD

Input to SEL Setup Time(2), (Figure 3 and Figure 4)

1.0

0.5

ns

TSWITCH

SEL to Switched Output, (Figure 3 and Figure 4)

0.9

1.2

1.7

ns

TPHZ

Disable Time (Active to TRI-STATE) High to Z, Figure 5

2.1

4.0

ns

TPLZ

Disable Time (Active to TRI-STATE) Low to Z, Figure 5

3.0

4.5

ns

TPZH

Enable Time (TRI-STATE to Active) Z to High, Figure 5

25.5

55.0

ns

TPZL

Enable Time (TRI-STATE to Active) Z to Low, Figure 5

25.5

55.0

ns

TLHT

Output Low-to-High Transition Time, 20% to 80%, Figure 7

290

400

580

ps

THLT

Output High-to-Low Transition Time, 80% to 20%, Figure 7

290

400

580

ps

(1)

The parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT (process,

voltage and temperature) range.

(2)

TSET and THOLD time specify that data must be in a stable state before and after the SEL transition.

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