VREC

VBIAS

VCOMP

VCC

VOUT

VGATE

xxxxxxx

xxxxxxx

t0

t1

t2

t3

t4 time

10.5V

7.5V

17.7V

13.5V

+

±

14

11

VCC

UVLO

8

LM3447

13.5V

4.2V

BIAS

VCC

GND

UVLO

AUX

NA

RBS

QPASS

RHLD1

CPFC

DZBS

RDAMP

CVCC

PRI

NP

Rectified AC Line

VREC(t)

+

10

7

COMP

GATE

PWM

CCOMP

(a)

(b)

LM3447

www.ti.com

SNOSC65 A – APRIL 2012 – REVISED MAY 2012

VCC BIAS SUPPLY AND START-UP

Figure 19. (a) Bias Circuit and (b) Typical Startup Waveforms

The LM3447 is designed to achieve instant turn-on using an external linear regulator circuit, shown in Figure 19

(a). The start-up sequence is internally controlled by the BIAS voltage and VCC undervoltage lockout (UVLO)

circuit and is illustrated in Figure 19 (b). The BIAS input is a low current voltage clamp circuit that provides a

reference to the linear pass transistor, QPASS. The clamp circuit current is set by connecting resistor, RBS,

between the input rectified AC voltage, VREC and BIAS. When power is applied, the BIAS voltage set to 17.7V

and the capacitor, CVCC is rapidly charged by transistor QPASS. Resistor RHLD1 is used to limit the maximum

allowable current, based on the safe operating area (SOA) rating of the transistor. The LM3447 starts operating

when VCC exceeds the UVLO rising threshold of 10.5V, after which the BIAS voltage is reduced to 13.5V. The

GATE drive output is enabled when the COMP voltage exceeds the minimum internal PWM ramp threshold of

280mV. As the output voltage, VOUT, increases, the bootstrap circuit based on an auxiliary winding of the

transformer is energized and begins delivering power to the device. At any time, if VCC falls below 7.5V the

device enters a UVLO state forcing BIAS to step back to 17.7V to initiate a new start-up sequence. The switching

of BIAS voltage between two thresholds, 17.7V to 13.5V, is performed in association with a large VCC UVLO

hysteresis of 3V to allow for a larger variation in auxiliary output voltage.

The key waveforms illustrating the bias circuit operation and start-up sequence under dimming are shown in

Figure 20. The impact of phase-cut dimming on BIAS, VOUT and VCC behavior is highlighted. The chopping of

the input voltage by an external dimmer causes the output voltage, VOUT, to vary along with LED current. As VCC

voltage tracks the output voltage, VOUT, it too fluctuates based on the dimming command. At low dimming levels,

UVLO is engaged as VCC falls below 7.5V and the BIAS switches to 17.7V, initiating a start-up sequence. The

BIAS behavior interacts with the external dimmer circuit, causing the device to enter into a re-start condition,

where VCC fluctuates between UVLO high and low thresholds. With this mode of operation, the LM3447 is

capable of providing quick response to any changes in the dimming command. In the case where the external

dimmer is switched off, VCC is discharged and all of the device operation is ceased. A new start-up cycle is

initiated, when the dimmer is switched on and the device responds in the manner illustrated in Figure 19 (b).

Copyright © 2012, Texas Instruments Incorporated

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